1. Field of the Invention
The present invention relates to the fabrication of integrated circuits. More particularly, the invention relates to a process for depositing dielectric layers on a substrate.
2. Background of the Invention
One of the primary steps in the fabrication of modern semiconductor devices is the formation of metal and dielectric films on a substrate by chemical reaction of gases. Such deposition processes are referred to as chemical vapor deposition or CVD. Conventional thermal CVD processes supply reactive gases to the substrate surface where heat-induced chemical reactions take place to produce a desired film. The high temperatures at which some thermal CVD processes operate can damage device structures having layers previously formed on the substrate. A preferred method of depositing metal and dielectric films at relatively low temperatures is plasma-enhanced CVD (PECVD) techniques such as described in U.S. Pat. No. 5,362,526, entitled “Plasma-Enhanced CVD Process Using TEOS for Depositing Silicon Oxide”. Plasma-enhanced CVD techniques promote excitation and/or disassociation of the reactant gases by the application of energy, commonly radio frequency (RF) energy, to a reaction zone near the substrate surface, thereby creating plasma of highly reactive species. The high reactivity of the species reduces the energy required for a chemical reaction to take place, and thus lowers the required temperature for such PECVD processes.
Semiconductor device geometries have dramatically decreased in size since such devices were first introduced several decades ago. Since then, integrated circuits have generally followed the two year/half-size rule (often called Moore's Law), which means that the number of devices that will fit on a chip doubles every two years. Today's fabrication plants are routinely producing devices having 0.35 μm and even 0.25 μm feature sizes, and tomorrow's semiconductor manufacturing facilities currently produce devices having even smaller geometries.
As devices geometries become smaller, liner layers and capping layers having relatively high dielectric constants contribute more to the overall dielectric constant of a multi-component dielectric layer. Additionally, the smaller device geometries result in an increase in parasitic capacitance between devices. Parasitic capacitance between metal interconnects on the same or adjacent layers on a device can result in crosstalk between the metal lines or interconnects and/or create resistance-capacitance (RC) delay, thereby reducing the response time of the device and degrading the overall performance of the device. The effects of parasitic capacitance between metal interconnects on the same or adjacent layers in the circuit is especially of concern as the current state of the art circuits can employ 4 to 5 levels of interconnection, while advanced devices require 6, 7, or possibly 8 levels of interconnection.
Lowering the parasitic capacitance between metal interconnects separated by dielectric material can be accomplished by increasing the thickness of the dielectric material, by lowering the dielectric constant of the dielectric material, or both. Increasing the thickness of the dielectric materials, however, does not address parasitic capacitance within the same metalized layer or plane. As a result, to reduce the parasitic capacitance between metal interconnects on the same or adjacent layers, one must change the material used between the metal lines or interconnects to a material having a lower dielectric constant than that of the materials currently used, i.e., K≈3.0.
Therefore, as the size of the semiconductor devices are reduced, an ultra low-K dielectric material is required for the interconnect structure. One integration challenge has been the adhesion strength between low-K dielectric materials and surface on which they are formed. Bad adhesion can cause several reliability issues, including electro migration (EM) failure, chip package interaction (CPI) failure, etc. One solution used to improve the adhesion of the low-K dielectric material is to implement an adhesion layer before the main bulk film deposition of the low or ultra K layer.
FIG. 1 illustrates a schematic diagram of a conventional low-K dielectric layer deposited on a substrate by the processes known in the art. The diagram shows an adhesive layer 50 disposed on an underlying layer 20. The adhesive layer 50 provides a bond between the bulk layer 40 and the underlying layer 20. The adhesion layer 50 is composed of a carbon-free oxide initiation layer 10 followed by a transition layer 30 with increasing carbon content steadily between the initiation layer 10 and bulk layer 40. However, if the thickness 55 of an adhesion layer 50 is too great, it will cause an unacceptable increase in the K value, especially at advanced node (<20 nm).
Referring to FIG. 1, the PECVD initiation layer 10 is deposited by the plasma enhanced reaction of a film containing carbon free silicon and oxide, one such compound is silica (SiO2). A transition or graded layer 30 is then deposited on the initiation layer 10 by the plasma enhanced reaction of gases containing silicon, carbon and oxygen, and the concentration of the carbon containing gas is increased as a carbon doped film layer is formed to the full thickness 55 of the adhesion layer 50. The full thickness 55 of the adhesion layer 50 is approximately greater than 350 Å (angstroms×10−10). A four point bending technique is used to measure fracture energy by applying a crack driving “force” that is higher than the cracking “resistance” of the weakest layer in the thin film stack. The fracture energy measured for the conventional low-K dielectric layer deposited on the substrate of FIG. 1 is approximately 6.2 J/m2. This fracture energy indicates a good adhesion but the adhesion layer 50 has a large thickness without even considering the remaining thickness of the low-K dielectric layer.
The key for successful low-K integration is to maintain a strong adhesion while maintaining a minimum thickness 55 of the adhesion layer 50 at the advanced node. Therefore, there remains a need for thin dielectric layers (<150 Å) having dielectric constants below 2.5 that also have good adhesion properties.